H扩散掺杂源漏的自对准顶栅a-IGZO TFT制备工艺研究
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摘要
采用氢(H)扩散掺杂源漏的方法对自对准顶栅a-IGZO TFT的制备工艺进行了研究。氢的扩散掺杂通过PECVD生长SiNx钝化层而实现。实验结果显示,在栅电极图形化后,是否继续进行栅介质刻蚀对器件性能有较大影响。对刻蚀了SiO_2栅介质层的器件,发现其泄漏电流较大,这可能是由于有源层侧壁的刻蚀残留物导致的;短沟道器件阈值电压偏负且在经过退火后迁移率减小,则是由于严重的H横向扩散导致的。对未刻蚀SiO_2栅介质层的器件,发现其阈值电压相对偏正,应该是因为SiO_2栅介质对H的掺杂有一定的阻挡作用,导致H的横向扩散得到了抑制;器件在经过退火后迁移率上升,开态电流增大,应该是因为未刻蚀栅介质中的H热扩散到下方的源漏区域,降低了源漏电阻。
The fabrication of self-aligned top gate a-IGZO TFT with source-drain doped by hydrogen diffusion was studied. The doping of hydrogen was achieved during the growth of SiN_x passivation layer by PECVD. The experimental results show that the performance of the device is greatly affected by the option for the gate dielectric etching following the gate electrode patterning. For the devices with gate dielectric layer etched, it is found that the leakage current is large, which may be caused by the etching residue on the side wall of active layer;The V_(TH) of short channel devices is negative and the mobility decreases after annealing, which is caused by the deep H lateral diffusion. For the devices without gate dielectric layer etched, it is found that the V_(TH) of devices is positive,because of the suppression of H lateral diffusion thanks to the inhibiting effect of SiO_2 gate dielectric on H doping.The on-state current and mobility of devices increases after annealing, which may be due to the entrance of H in gate dielectric to the source and drain area by thermal diffusion, reducing resistance of source and drain area.
The fabrication of self-aligned top gate a-IGZO TFT with source-drain doped by hydrogen diffusion was studied. The doping of hydrogen was achieved during the growth of SiN_x passivation layer by PECVD. The experimental results show that the performance of the device is greatly affected by the option for the gate dielectric etching following the gate electrode patterning. For the devices with gate dielectric layer etched, it is found that the leakage current is large, which may be caused by the etching residue on the side wall of active layer;The V_(TH) of short channel devices is negative and the mobility decreases after annealing, which is caused by the deep H lateral diffusion. For the devices without gate dielectric layer etched, it is found that the V_(TH) of devices is positive,because of the suppression of H lateral diffusion thanks to the inhibiting effect of SiO_2 gate dielectric on H doping.The on-state current and mobility of devices increases after annealing, which may be due to the entrance of H in gate dielectric to the source and drain area by thermal diffusion, reducing resistance of source and drain area.
引文
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[2] Bae J U, Kim D H, Kim K, et al. Development of Oxide TFT's Structures[C]//SID Symposium Digest of Technical Papers, Blackwell Publishing Ltd, 2013, 44(1): 89-92.
[3] Geng D, Kang D H, Man J S, et al. High-speed and Low-Voltage-Driven Shift Register With Self-Aligned Coplanar a-IGZOTFTs[J].IEEE Electron Device Letters,2012, 33(33): 1012-1024.
[4] Park J, Song I, Kim S, et al. Self-Aligned Top-Gate Amorphous Gallium Indium Zinc Oxide Thin Film Transistors[J]. Applied Physics Letters, 2008, 93(5):053501.
[5] Kim S, Park J,Kim C, et al. Source/Drain Formation of Self-Aligned Top-Gate Amorphous GaInZnO Thin-Film Transistors by NH3 Plasma Treatment[J]. Electron Device Letters IEEE, 2009,30(4):374-376.
[6] Park J, Song I, Kim S, et al. Self-Aligned Top-Gate Amorphous Gallium Indium Zinc Oxide Thin Film Transistors[J]. Applied Physics Letters,2008,93(5):053501.
[7] Liu S E, Yu M J, Lin C Y, et al. Influence of Passivation Layers on Characteristics of a-InGaZnO Thin-Film Transistors[J]. IEEE Electron Device Letters,2011,32(2):161-163.
[8] Ye Z, Lu L, Man W. Zine-Oxide Thin-Film Transistor With Self-Aligned Source/Drain Region Doped With Implanted Boron For Enhanced Thermal Stability[J]. IEEE Transactions on Electron Device,2012,59(2):393-399.
[9] Morosawa N,Ohshima Y,Morooka M,et al. Novel Self-aligned top-gate oxide TFT for AMOLED Displays[J].Journal of the Society for Information Display,2012,20(1):47-52.
[10] Chern J G J, Chang P, Motta R F, et al. A New Method to Determine MOSFET Channel Length[J]. IEEE Electron Device Letters,1980,1(9):170-173.
[11] Suresh A, Muth J F. Bias stress stability of indium gallium zinc oxide channel based transparent thin film transistors[J]. Applied Physics Letters, 2008, 92(3): 033502.
[12] Lee J, Park J S, Pyo Y S, et al. The influence of the gate dielectrics on threshold voltage instability in amorphous indium-gallium-zinc oxide thin film transistors[J]. Applied Physics Letters, 2009, 95(12): 3502.