一款消除浮空点并自锁存的老化预测传感器
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摘要
针对负偏置温度不稳定性引起的组合逻辑电路老化,提出了一款消除浮空点并自锁存的老化预测传感器。该传感器不仅可以预测组合逻辑电路老化,而且能够通过传感器内部的反馈来锁存检测结果,同时解决稳定性校验器在锁存期间的浮空点问题,其延时单元为可控型延时单元,可以控制其工作状态。使用HSPICE软件进行仿真,验证了老化预测传感器的可行性,可以适用于多种环境中且不会影响传感器性能。与同类型结构相比,该传感器的稳定性校验器能够对检测结果进行自锁存,使用的晶体管数量减少了约8%,平均功耗降低了约20%。
Aiming at the aging of combinational logic circuits caused by negative bias temperature instability, a floating point eliminated and self-latching aging prediction sensor was proposed. The sensor can predict the aging of the combinational logic circuit, and can latch the detection result through the feedback inside the sensor. Meanwhile, it can solve the floating point problem of the stability checker during latching. Delay unit of the sensor is controllable delay unit, which can control its working state. HSPICE simulation results show that the sensor is feasible and can be used in many environments without affecting the performance of the sensor. Compared with the same type of structure, the stability checker of the sensor can latch up the predicted results, the number of transistors used in the sensor is reduced by about 8%, and average power consumption is reduced by about 20%.
Aiming at the aging of combinational logic circuits caused by negative bias temperature instability, a floating point eliminated and self-latching aging prediction sensor was proposed. The sensor can predict the aging of the combinational logic circuit, and can latch the detection result through the feedback inside the sensor. Meanwhile, it can solve the floating point problem of the stability checker during latching. Delay unit of the sensor is controllable delay unit, which can control its working state. HSPICE simulation results show that the sensor is feasible and can be used in many environments without affecting the performance of the sensor. Compared with the same type of structure, the stability checker of the sensor can latch up the predicted results, the number of transistors used in the sensor is reduced by about 8%, and average power consumption is reduced by about 20%.
引文
[1] DING D L, ZHANG Y J, WANG P J, et al. Design a delay amplified digital aging sensor circuit in 65 nm CMOS[C]// Proceedings of the 13th IEEE International Conference on Solid-State and Integrated Circuit Technology. Hangzhou, China, 2016 : 1449-1451.
[2] VAIDYANATHAN B, OATES A S. Technology scaling effect on the relative impact of NBTI and process variation on the reliability of digital circuits [J]. IEEE Transactions on Device and Materials Reliability, 2012, 12(2):428-436.
[3] KHAN S, HAMDIOUI S. Modeling mitigating NBTI in nanoscale circuits[C]// Proceedings of IEEE 17th International On-Line Testing Symposium. Athens, Greece, 2011: 1-6.
[4] LIN I C, LIN C H, LI K H. Leakage and aging optimization using transmission gate-based technique[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(1):87-99.
[5] KHACHATRYAN A. A novel aging sensor with programmable resolution[C]// Proceedings of the IEEE East-West Design & Test Symposium. Novi Sad, Serbia, 2017: 1-4.
[6] TAJIMA S, TOGAWA N, YANAGISAWA M, et al. Soft error tolerant latch designs with low power consumption (invited paper) [C]// Proceedings of the 12th International Conference on ASIC. Guiyang, China , 2017:52-55.
[7] 靳松,韩银和,李华伟,等.考虑工作负载影响的电路老化预测方法[J].计算机辅助设计与图形学学报,2010,22(12): 2242-2249.JIN S, HAN Y H, LI H W, et al. On predicting circuit aging via considering actual workload [J]. Journal of Computer-Aided Design & Computer Graphics, 2010, 22(12): 2242-2249(in Chinese).
[8] OMANA M, ROSSI D, BOSIO N, et al. Low cost NBTI degradation detection and masking approaches [J]. IEEE Transactions on Computers, 2013, 62(3):496-509.
[9] 徐辉,何洋,李丹青,等.考虑路径相关性的TG-based缓解电路老化[J].电子测量与仪器学报, 2018, 32(4): 187-192.XU H, HE Y, LI D Q, et al. TG-based mitigation of circuits aging considering path correlation[J]. Journal of Electronic Measurement and Instrument, 2018, 32(4): 187-192(in Chinese).
[10] SEMI?O J, SARAIVA D, LEONG C, et al. Performance sensor for tolerance and predictive detection of delay-faults[C]// Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. Amsterdam, Netherlands 2014: 110-115.
[11] MARTINS C V, SEMI?O J, VAZQUEZ J C, et al. Adaptive error-prediction flip-flop for performance failure prediction with aging sensors[C]//Proceedings of the 29th VLSI Test Symposium. Dana Point, USA, 2011: 203-208.
[12] AGARWAL M, PAUL B C, ZHANG M, et al. Circuit failure prediction and its application to transistor aging[C]// Proceedings of the 25th IEEE IEEE VLSI Test Symposium. Berkeley, CA, USA, 2007: 277-286.
[13] VAZQUEZ J C, CHAMPAC V, ZIESEMER A M, et al.Predictive error detection by on-line aging monitoring[C]//Proceedings of the 16th International On-Line Testing Symposium. Corfu, Greece , 2010: 9-14.
[14] AMINI-SHEHSDEH Z, NABAVI A. A novel sensor for prediction of aging failure[C]// Proceedings of the 3rd International Conference on Computational Intelligence, Modelling & Simulation. Langkawi, Malaysia, 2011: 399-403.
[15] CAO Y, ZHAO W. Predictive technology model for nano-CMOS design exploration[C]//Proceedings of the 1st International Conference on Nano-Networks and Workshops. Lausanne, Switzerland, 2006: 1-5.
[2] VAIDYANATHAN B, OATES A S. Technology scaling effect on the relative impact of NBTI and process variation on the reliability of digital circuits [J]. IEEE Transactions on Device and Materials Reliability, 2012, 12(2):428-436.
[3] KHAN S, HAMDIOUI S. Modeling mitigating NBTI in nanoscale circuits[C]// Proceedings of IEEE 17th International On-Line Testing Symposium. Athens, Greece, 2011: 1-6.
[4] LIN I C, LIN C H, LI K H. Leakage and aging optimization using transmission gate-based technique[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(1):87-99.
[5] KHACHATRYAN A. A novel aging sensor with programmable resolution[C]// Proceedings of the IEEE East-West Design & Test Symposium. Novi Sad, Serbia, 2017: 1-4.
[6] TAJIMA S, TOGAWA N, YANAGISAWA M, et al. Soft error tolerant latch designs with low power consumption (invited paper) [C]// Proceedings of the 12th International Conference on ASIC. Guiyang, China , 2017:52-55.
[7] 靳松,韩银和,李华伟,等.考虑工作负载影响的电路老化预测方法[J].计算机辅助设计与图形学学报,2010,22(12): 2242-2249.JIN S, HAN Y H, LI H W, et al. On predicting circuit aging via considering actual workload [J]. Journal of Computer-Aided Design & Computer Graphics, 2010, 22(12): 2242-2249(in Chinese).
[8] OMANA M, ROSSI D, BOSIO N, et al. Low cost NBTI degradation detection and masking approaches [J]. IEEE Transactions on Computers, 2013, 62(3):496-509.
[9] 徐辉,何洋,李丹青,等.考虑路径相关性的TG-based缓解电路老化[J].电子测量与仪器学报, 2018, 32(4): 187-192.XU H, HE Y, LI D Q, et al. TG-based mitigation of circuits aging considering path correlation[J]. Journal of Electronic Measurement and Instrument, 2018, 32(4): 187-192(in Chinese).
[10] SEMI?O J, SARAIVA D, LEONG C, et al. Performance sensor for tolerance and predictive detection of delay-faults[C]// Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. Amsterdam, Netherlands 2014: 110-115.
[11] MARTINS C V, SEMI?O J, VAZQUEZ J C, et al. Adaptive error-prediction flip-flop for performance failure prediction with aging sensors[C]//Proceedings of the 29th VLSI Test Symposium. Dana Point, USA, 2011: 203-208.
[12] AGARWAL M, PAUL B C, ZHANG M, et al. Circuit failure prediction and its application to transistor aging[C]// Proceedings of the 25th IEEE IEEE VLSI Test Symposium. Berkeley, CA, USA, 2007: 277-286.
[13] VAZQUEZ J C, CHAMPAC V, ZIESEMER A M, et al.Predictive error detection by on-line aging monitoring[C]//Proceedings of the 16th International On-Line Testing Symposium. Corfu, Greece , 2010: 9-14.
[14] AMINI-SHEHSDEH Z, NABAVI A. A novel sensor for prediction of aging failure[C]// Proceedings of the 3rd International Conference on Computational Intelligence, Modelling & Simulation. Langkawi, Malaysia, 2011: 399-403.
[15] CAO Y, ZHAO W. Predictive technology model for nano-CMOS design exploration[C]//Proceedings of the 1st International Conference on Nano-Networks and Workshops. Lausanne, Switzerland, 2006: 1-5.