针对抗老化门替换技术的关键门识别算法
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摘要
为解决现有门替换技术应用中存在的时延仿真不精确和关键门选取冗余问题,对时序分析方法进行改进,通过引入电路内部节点信息,准确预测电路NBTI老化.然后,提出了一种门替换技术应用下的关键门识别算法,定义了表征门电路抗NBTI老化能力的度量公式,将其作为电路老化关键门的识别依据,用于提高关键门识别精度和效率.基于45 nm PTM工艺库和ISCAS85基准电路的仿真结果表明,应用改进门替换技术进行电路抗NBTI老化设计得到的电路时延退化改善率平均值为25.11%,较现有方案提高13.24%,而反映硬件开销的平均门替换率仅为5.82%,明显低于现有方案的11.95%.因此,所提方案仅以较低的硬件开销便可获得较好的门替换技术抗老化效果.
To solve the problems of inaccurate delay simulation and redundant critical gate selection in the application of the existing gate replacement technology,a circuit timing analysis method is improved to accurately predict the NBTI( negative bias temperature instability) aging of circuits by introducing the information of the internal nodes. Then,a critical gate identification algorithm for the application of the gate replacement technology is proposed. A measure formula for characterizing the anti-NBTI aging ability of gate circuits is defined and served as a basis for identifying the circuit critical gate to improve the accuracy and the efficiency of critical gate identification. The simulation results based on 45 nm PTM( predictive transistor model) and ISCAS85 benchmark circuits show that the improvement rate of circuit delay degradation using the improved anti-NBTI aging scheme is25. 11%,which is 13. 24% higher than that of the existing one. How ever,the average gate replacement rate representing the hardware cost is only 5. 82%,which is significantly low er than that of the existing schemes( 11. 95%). The proposed scheme can obtain good anti-aging effect of the gate replacement technology with low hardware overhead.
To solve the problems of inaccurate delay simulation and redundant critical gate selection in the application of the existing gate replacement technology,a circuit timing analysis method is improved to accurately predict the NBTI( negative bias temperature instability) aging of circuits by introducing the information of the internal nodes. Then,a critical gate identification algorithm for the application of the gate replacement technology is proposed. A measure formula for characterizing the anti-NBTI aging ability of gate circuits is defined and served as a basis for identifying the circuit critical gate to improve the accuracy and the efficiency of critical gate identification. The simulation results based on 45 nm PTM( predictive transistor model) and ISCAS85 benchmark circuits show that the improvement rate of circuit delay degradation using the improved anti-NBTI aging scheme is25. 11%,which is 13. 24% higher than that of the existing one. How ever,the average gate replacement rate representing the hardware cost is only 5. 82%,which is significantly low er than that of the existing schemes( 11. 95%). The proposed scheme can obtain good anti-aging effect of the gate replacement technology with low hardware overhead.
引文
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[8]梁华国,陶志勇,李扬.一种缓解NBTI效应引起电路老化的门替换方法[J].电子测量与仪器学报,2013,27(11):1011-1017.DOI:103724/SP.J.1187.2013.01011.Liang Huaguo,Tao Zhiyong,Li Yang.Efficient method to mitigate NBTI-induced circuit degradation by gate replacement techniques[J].Journal of Electronic Measurement and Instrument,2013,27(11):1011-1017.DOI:103724/SP.J.1187.2013.01011.(in Chinese)
[9]Lorenz D,Georgakos G,Schlichtmann U.Aging analysis of circuit timing considering NBTI and HCI[C]//2009 15th IEEE International On-Line Testing Symposium.Lisbon,Portugal,2009:3-8.DOI:10.1109/IOLTS.2009.5195975.
[10]Bhardwaj S,Wang W,Vattikonda R,et al.Scalable model for predicting the effect of negative bias temperature instability for reliable design[J].IET Circuits,Devices&Systems,2008,2(4):361-371.DOI:10.1049/iet-cds:20070225.
[11]Cao Y,Velamala J,Sutaria K,et al.Cross-layer modeling and simulation of circuit reliability[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2014,33(1):8-23.DOI:10.1109/tcad.2013.2289874.
[12]Wang Y,Luo H,He K,et al.Temperature-aware NBTI modeling and the impact of input vector control on performance degradation[C]//2007 IEEE Design,Automation&Test in Europe Conference&Exhibition.Nice,France,2007:1-6.DOI:10.1109/DATE.2007.364650.
[13]Chen J,Wang S,Tehranipoor M.Efficient selection and analysis of critical-reliability paths and gates[C]//Proceedings of the G reat Lakes Symposium on VLSI.Salt Lake City,Utah,USA,2012:45-50.
[2]Wang S,Du G,Lin X.An analytical model for negative bias temperature instability[C]//2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.Shanghai,China,2010:1686-1688.DOI:10.1109/icsict.2010.5667291.
[3]Wang Y,Chen X,Wang W,et al.On the efficacy of input Vector Control to mitigate NBTI effects and leakage pow er[C]//IEEE International Symposium on Quality of Electronic Design.San Jose,CA,USA,2009:19-26.
[4]Lin I C,Li K H,Lin C H,et al.NBTI and leakage reduction using ILP-based approach[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2014,22(9):2034-2038.DOI:10.1109/tvlsi.2013.2280651.
[5]Wang Y,Chen X,Wang W,et al.Leakage power and circuit aging cooptimization by gate replacement techniques[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2011,19(4):615-628.DOI:10.1109/tvlsi.2009.2037637.
[6]Ghane M,Zarandi H R.Gate merging:An NBTI mitigation method to eliminate critical internal nodes in digital circuits[C]//2016 24th IEEE Euromicro International Conference on Parallel,Distributed,and Network-Based Processing.Heraklion,Greece,2016:786-791.DOI:10.1109/pdp.2016.90.
[7]Wu K C,Marculescu D.Joint logic restructuring and pin reordering against NBTI-induced performance degradation[C]//IEEE Design,Automation&Test in Europe Conference&Exhibition.Nice,France.2009:75-80.
[8]梁华国,陶志勇,李扬.一种缓解NBTI效应引起电路老化的门替换方法[J].电子测量与仪器学报,2013,27(11):1011-1017.DOI:103724/SP.J.1187.2013.01011.Liang Huaguo,Tao Zhiyong,Li Yang.Efficient method to mitigate NBTI-induced circuit degradation by gate replacement techniques[J].Journal of Electronic Measurement and Instrument,2013,27(11):1011-1017.DOI:103724/SP.J.1187.2013.01011.(in Chinese)
[9]Lorenz D,Georgakos G,Schlichtmann U.Aging analysis of circuit timing considering NBTI and HCI[C]//2009 15th IEEE International On-Line Testing Symposium.Lisbon,Portugal,2009:3-8.DOI:10.1109/IOLTS.2009.5195975.
[10]Bhardwaj S,Wang W,Vattikonda R,et al.Scalable model for predicting the effect of negative bias temperature instability for reliable design[J].IET Circuits,Devices&Systems,2008,2(4):361-371.DOI:10.1049/iet-cds:20070225.
[11]Cao Y,Velamala J,Sutaria K,et al.Cross-layer modeling and simulation of circuit reliability[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2014,33(1):8-23.DOI:10.1109/tcad.2013.2289874.
[12]Wang Y,Luo H,He K,et al.Temperature-aware NBTI modeling and the impact of input vector control on performance degradation[C]//2007 IEEE Design,Automation&Test in Europe Conference&Exhibition.Nice,France,2007:1-6.DOI:10.1109/DATE.2007.364650.
[13]Chen J,Wang S,Tehranipoor M.Efficient selection and analysis of critical-reliability paths and gates[C]//Proceedings of the G reat Lakes Symposium on VLSI.Salt Lake City,Utah,USA,2012:45-50.