一种基于斯格明子介质的高效存内计算框架
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摘要
存内计算(processing in memory, PIM)作为一种新兴的技术,支持数据在存储单元内就地处理,减少了数据的移动并增加了数据的并行处理,在一定程度上弥补了冯·诺依曼架构的缺陷.和传统易失随机存储介质相比,赛道型内存(racetrack memory, RM)具有密度大、非易失且静态功耗低等特点,支持高效的存内计算.为解决性能与功耗问题,提出了一种新型的基于斯格明子(Skyrmion)介质的非易失性存内计算框架.该框架采用斯格明子赛道内存(Skyrmion-based racetrack memory)作为存储单元,采用斯格明子逻辑门(Skyrmion-based logic gate)构成的加法/乘法器组成计算单元,无须大量CMOS(complementary metal oxide semiconductor)电路辅助,设计复杂度大大降低.同时,通过在电路级优化存储单元读写端口数目与在系统级改进内存地址映射方式,大幅提高该框架的运行效率.实验结果表明:相比基于磁畴壁(domain-wall)的非易失性存内计算框架,提出的框架在运行时间上节省了48.1%,同时在能耗上节省了42.9%.
As a new computing paradigm, processing in memory(PIM) allows the parallel computation in both processors and memories, which drastically reduce the movements between computation units and storage units. Therefore, PIM can be considered as an efficient technology to somewhat address the shortcomings of the von neumann architecture. Compared with traditional random access memories, racetrack memory has many merits including high density, non-volatility, and low static power. Therefore, it can be used for efficient PIM computing. To address the shortages of domain-wall based PIM, this paper proposes a novel PIM framework based on the Skyrmion material. In this framework, we use Skyrmion-based racetrack memories to construct storage units, and use Skyrmion-based logic gates to compose both adders and multipliers for the computation units. Since our framework does not need CMOS(complementary metal oxide semiconductor) circuits to assist the underlying computation unit construction, the design complexity is significantly reduced. Meanwhile, based on our proposed optimization methods for read and write operations at the circuit layer and address mapping mode of the memory at the system level, the performance of our framework is drastically improved. Experimental results show that compared with domain-wall based PIM framework, our approach can achieve 48.1% time improvement and 42.9% energy savings on average.
As a new computing paradigm, processing in memory(PIM) allows the parallel computation in both processors and memories, which drastically reduce the movements between computation units and storage units. Therefore, PIM can be considered as an efficient technology to somewhat address the shortcomings of the von neumann architecture. Compared with traditional random access memories, racetrack memory has many merits including high density, non-volatility, and low static power. Therefore, it can be used for efficient PIM computing. To address the shortages of domain-wall based PIM, this paper proposes a novel PIM framework based on the Skyrmion material. In this framework, we use Skyrmion-based racetrack memories to construct storage units, and use Skyrmion-based logic gates to compose both adders and multipliers for the computation units. Since our framework does not need CMOS(complementary metal oxide semiconductor) circuits to assist the underlying computation unit construction, the design complexity is significantly reduced. Meanwhile, based on our proposed optimization methods for read and write operations at the circuit layer and address mapping mode of the memory at the system level, the performance of our framework is drastically improved. Experimental results show that compared with domain-wall based PIM framework, our approach can achieve 48.1% time improvement and 42.9% energy savings on average.
引文
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[14]Zhang Xichao,Ezawa M,Zhou Yan.Magnetic Skyrmion logic gates:Conversion,duplication and merging of Skyrmions[J/OL].Scientific Reports,2015:Article number 9400.[2018-08-02].https://www.nature.com/articles/srep09400
[15]Xing Xiangjun,Pong Philip,Zhou Yan.Skyrmion domain wall collision and domain wall-gated Skyrmion logic[J].Physical Review B,2016,94(5):054408
[16]Sun Guangyu,Zhang Chao,Li Hehe,et al.From device to system:Cross-layer design exploration of racetrack memory[C]//Proc of the Design,Automation and Test in Europe.San Jose,CA:EDA Consortium,2015:1018-1023
[17]Jeong M K,Yoon D H,Sunwoo D,et al.Balancing DRAMlocality and parallelism in shared memory CMP systems[C]//Proc of the High Performance Computer Architecture(HPCA).Piscataway,NJ:IEEE,2012:1-12
[18]Kang Wang,Huang Yangqi,Zheng Chentian,et al.Voltage controlled magnetic Skyrmion motion for racetrack memory[J/OL].Scientific Reports,2016:Article number 23164.[2018-08-02].https://www.nature.com/articles/srep23164
[19]Binkert N,Beckmann B,Black G,et al.The Gem5simulator[J].ACM SIGARCH Computer Architecture News,2011,39(2):1-7
[20]Li Sheng,Ahn J H,Strong R D,et al.McPAT:An integrated power,area,and timing modeling framework for multicore and manycore architectures[C]//Proc of the Annual IEEE/ACM Int Symp on Microarchitecture.Piscataway,NJ:IEEE,2009:469-480
[21]Dong Xiangyu,Xu Cong,Jouppi N,et al.NVSim:Acircuit-level performance,energy,and area model for emerging non-volatile memory[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2012,31(7):994-1007
[2]Gokhale M,Holmes B,Iobst K.Processing in memory:The Terasys massively parallel PIM array[J].Computer,1995,28(4):23-31
[3]Zhang Dongping,Jayasena N,Lyashevsky A,et al.TOP-PIM:Throughput-oriented programmable processing in memory[C]//Proc of the 23rd ACM Int Symp on HighPerformance Parallel and Distributed Computing.New York:ACM,2014:85-98
[4]Akin B,Franchetti F,Hoe J C.Data reorganization in memory using 3D-stacked DRAM[J].ACM SIGARCHComputer Architecture News,2015,43(3):131-143
[5]Joshi M,Zhang Wangyuan,Li Tao.Mercury:A fast and energy-efficient multi-level cell based phase change memory system[C]//Proc of the 17th High Performance Computer Architecture(HPCA).Piscataway,NJ:IEEE,2011:345-356
[6]Kültürsay E,Kandemir M,Sivasubramaniam A,et al.Evaluating STT-RAM as an energy-efficient main memory alternative[C]//Proc of the Performance Analysis of Systems and Software(ISPASS).Piscataway,NJ:IEEE,2013:256-267
[7]Lee B C,Ipek E,Mutlu O,et al.Architecting phase change memory as a scalable DRAM alternative[J].ACMSIGARCH Computer Architecture News,2009,37(3):2-13
[8]Parkin S,Yang Seehun.Memory on the racetrack[J].Nature Nanotechnology,2015,10(3):195-198
[9]Mao Mengjie,Wen Wujie,Zhang Yaojun,et al.Exploration of GPGPU register file architecture using domain-wall-shiftwrite based racetrack memory[C]//Proc of the 51st Annual Design Automation Conf.New York:ACM,2014:1-6
[10]Hu Qingda,Sun Guangyu,Shu Jiwu,et al.Exploring main memory design based on racetrack memory technology[C]//Proc of the 26th Great Lakes Symp on VLSI.Piscataway,NJ:IEEE,2016:397-402
[11]Yu Hao,Wang Yuhao,Chen Shuai,et al.Energy efficient in-memory machine learning for data intensive imageprocessing by non-volatile domain-wall memory[C]//Proc of the 19th Asia and South Pacific Design Automation Conf(ASP-DAC).Piscataway,NJ:IEEE,2014:191-196
[12]Fert A,Cros V,Sampaio J.Skyrmions on the track[J].Nature Nanotechnology,2013,8(3):152-156
[13]Tomasello R,Martinez E,Zivieri R,et al.A strategy for the design of Skyrmion racetrack memories[J/OL].Scientific Reports,2014:Article number 6784.[2018-08-02].https://www.nature.com/articles/srep06784
[14]Zhang Xichao,Ezawa M,Zhou Yan.Magnetic Skyrmion logic gates:Conversion,duplication and merging of Skyrmions[J/OL].Scientific Reports,2015:Article number 9400.[2018-08-02].https://www.nature.com/articles/srep09400
[15]Xing Xiangjun,Pong Philip,Zhou Yan.Skyrmion domain wall collision and domain wall-gated Skyrmion logic[J].Physical Review B,2016,94(5):054408
[16]Sun Guangyu,Zhang Chao,Li Hehe,et al.From device to system:Cross-layer design exploration of racetrack memory[C]//Proc of the Design,Automation and Test in Europe.San Jose,CA:EDA Consortium,2015:1018-1023
[17]Jeong M K,Yoon D H,Sunwoo D,et al.Balancing DRAMlocality and parallelism in shared memory CMP systems[C]//Proc of the High Performance Computer Architecture(HPCA).Piscataway,NJ:IEEE,2012:1-12
[18]Kang Wang,Huang Yangqi,Zheng Chentian,et al.Voltage controlled magnetic Skyrmion motion for racetrack memory[J/OL].Scientific Reports,2016:Article number 23164.[2018-08-02].https://www.nature.com/articles/srep23164
[19]Binkert N,Beckmann B,Black G,et al.The Gem5simulator[J].ACM SIGARCH Computer Architecture News,2011,39(2):1-7
[20]Li Sheng,Ahn J H,Strong R D,et al.McPAT:An integrated power,area,and timing modeling framework for multicore and manycore architectures[C]//Proc of the Annual IEEE/ACM Int Symp on Microarchitecture.Piscataway,NJ:IEEE,2009:469-480
[21]Dong Xiangyu,Xu Cong,Jouppi N,et al.NVSim:Acircuit-level performance,energy,and area model for emerging non-volatile memory[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2012,31(7):994-1007
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