基于0.13μm CMOS工艺的K波段SPDT开关
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摘要
基于130 nm CMOS工艺,设计了一种24 GHz工作频率的单刀双掷(SPDT)开关。该开关基于π型阻抗匹配网络,将浮体技术和堆叠晶体管结构应用于开关的并联臂、串联臂,实现了低插入损耗、高隔离度和高线性度。仿真结果表明,该SPDT开关的插入损耗S_(21)的-1.5 dB带宽为20～26 GHz。在20～26 GHz频率范围内,输入回波损耗S_(11)小于-18 dB,输出回波损耗S_(22)小于-17 dB,隔离度S_(12)大于32.2 dB。在频率24.5 GHz处,S_(21)可达-1.45 dB,输入1 dB压缩点为17.36 dBm。
A single pole double throw(SPDT) switch working at 24 GHz was designed in a 130 nm CMOS process. This SPDT switch was based on π-type impedance matching network, and the stacked transistors structure as well as the body floating technique were adopted in the shunt transistors and serial transistors to realize low insertion loss, high isolation and high linearity. The simulation results showed that the-1.5 dB bandwidth of insertion loss(S_(21)) was from 20 to 26 GHz. The input return loss(S_(11)) was less than-18 dB, the output return loss(S_(22)) was less than-17 dB, and the isolation(S_(12)) was better than 32.2 dB at the frequency range of 20 to 26 GHz. The input 1 dB compression point was 17.36 dBm at 24.5 GHz, and the S_(21 )achieved-1.45 dB.
A single pole double throw(SPDT) switch working at 24 GHz was designed in a 130 nm CMOS process. This SPDT switch was based on π-type impedance matching network, and the stacked transistors structure as well as the body floating technique were adopted in the shunt transistors and serial transistors to realize low insertion loss, high isolation and high linearity. The simulation results showed that the-1.5 dB bandwidth of insertion loss(S_(21)) was from 20 to 26 GHz. The input return loss(S_(11)) was less than-18 dB, the output return loss(S_(22)) was less than-17 dB, and the isolation(S_(12)) was better than 32.2 dB at the frequency range of 20 to 26 GHz. The input 1 dB compression point was 17.36 dBm at 24.5 GHz, and the S_(21 )achieved-1.45 dB.
引文
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[2] CAMPBELL C F,DUMKA D C.Wideband high power GaN on SiC SPDT switch MMICs [C] // IEEE MTT-S Int Microwave Symp.Anaheim,CA,USA.2010:23-28.
[3] LI W J,MA K X,MOU S X.A Ku-band high-isolation SPDT switch in 0.35 μm SiGe BiCMOS technology [C] // Int Symp Integr Circ.Singapore.2016:1-4.
[4] WANG S,LI Z K.A 6-32 GHz T/R switch in 0.18-μm CMOS technology [J].IEICE Elec Expr,2012,9(6):590-595.
[5] OU C Y,HSU C Y,LIN H R,et al.A high-isolation high-linearity 24-GHz CMOS T/R switch in the 0.18-μm CMOS process [C] // EuMA.Rome,Italy.2009:250-253.
[6] HE J,ZHANG Y P,YEO K S,et al.A comparative study of two techniques for improving power-handling capability of CMOS T/R switches [J].Int J RF & Microwave Comput Aided Engineer,2010,20(3):298-305.
[7] HE J,ZHANG Y P,XIONG Y Z.A 60-GHz single-pole- single-throw switch in 65-nm bulk CMOS [J].Int J RF & Microwave Comput Aided Engineer,2011,21(2):190-198.
[8] PRABIR K S,JONATHAN P C,WEI-MIN L K,et al.A K-band nMOS SPDT switch and phase shifter implemented in 130 nm SiGe BiCMOS technology [C] // IEEE Silicon Monol Integr Circ RF Syst.San Diego,CA,USA.2009:1-4.
[9] MOU S X,MA K X,YEO K S.A DC to 30 GHz ultra-wideband CMOS T/R switch [C] // Semiconductor Conf Dresden.Dresden,Germany.2011:1-4.