65nm闪存芯片擦除时间退化的优化设计
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摘要
随着制造工艺进入65nm节点,闪存的可靠性问题也越来越突出,其中闪存芯片擦除速度随着擦写循环的增加出现明显退化。该文从单个存储器件的擦写退化特性入手,详细讨论了隧穿氧化层缺陷的产生原因、对器件性能的影响及其导致整个芯片擦除时间退化的内在机理,并提出针对性的优化方案:采用阶梯脉冲电压擦写方式减缓存储单元退化;对非选中区块进行字线浮空偏置以抑制擦除时的阵列干扰。该文基于65 nm NOR Flash工艺平台开发了128 Mb闪存芯片,并对该方案进行了验证,测试结果表明,采用优化设计方案的芯片经过10万次擦写后的Sector擦除时间为104.9 ms,较采用常规方案的芯片(大于200 ms)具有明显的提升。
With the rapid development of microelectronics manufacture process, the reliability of flash memory has become more and more significant especially beyond 65 nm technology node. One of the most critical reliability issues is that the erase speed of flash memory chip degrades obviously with the increase of erase cycle. In this paper, the erasure degradation characteristics of flash cell were carefully reviewed. The generation mechanism of the tunneling oxide defect and its effects on device performance degradation are also well discussed. The optimization schemes are then proposed in this paper, including low stress program/erase scheme with staircase pulse and disturb-immune array bias condition for the unselected Sectors. A 128 Mb flash memory chip is developed based on SMIC 65 nm NOR flash technology to verify the optimization schemes. The testing results show that the Sector erase time of the optimized chip after 105 program/erase cycles is 104.9 ms, which is obviously improved compared with that of the conventional flash chip(more than 200 ms).
With the rapid development of microelectronics manufacture process, the reliability of flash memory has become more and more significant especially beyond 65 nm technology node. One of the most critical reliability issues is that the erase speed of flash memory chip degrades obviously with the increase of erase cycle. In this paper, the erasure degradation characteristics of flash cell were carefully reviewed. The generation mechanism of the tunneling oxide defect and its effects on device performance degradation are also well discussed. The optimization schemes are then proposed in this paper, including low stress program/erase scheme with staircase pulse and disturb-immune array bias condition for the unselected Sectors. A 128 Mb flash memory chip is developed based on SMIC 65 nm NOR flash technology to verify the optimization schemes. The testing results show that the Sector erase time of the optimized chip after 105 program/erase cycles is 104.9 ms, which is obviously improved compared with that of the conventional flash chip(more than 200 ms).
引文
[1]HONG S.Memory technology trend and future challenges[C]//International Electron Devices Meeting.[S.l.]:IEEE,2010:10.1109/IEDM.2010.5703348.
[2]YOSHIKAWA K,YAMADA S,MIYAMOTO J,et al.Comparison of current flash EEPROM erasing methods:Stability and how to control[C]//International Electron Devices Meeting.[S.l.]:IEEE,1992,93(74):595-598.
[3]WEI Dai-long,CAO Zi-gui,TANG Zhi-lin.An effective approach to improve split-gate flash product data retention[J].Journal of Semiconductor,2017,38(10):107-110.
[4]HEINRICH-BARNA S,DUNN C,VERRET D.Low temperature endurance failures on flash memory[C]//International Symposium on Quality Electronic Design.[S.l.]:IEEE,2017:87-92.
[5]SUN Zhong,ZHANG Man-hong,HUO Zong-liang.et al.Effect of damage in source and drain on the endurance of a65-nm-Node NOR flash memory[J].IEEE Transactions on Electron Devices,2013,12(60):3989-3995.
[6]TORRENTE G,COIGNUS J,VERNHET A,et al.Microscopic analysis of erase-induced degradation in 40 nm NOR flash technology[J].IEEE Transactions on Device and Materials Reliability,2016,4(16):597-603.
[7]SIKORA A,PESL F P,UNGER W.Technologies and reliability of modern embedded flash cells[J].Microelectronics Reliability,2006,46(12):1980-2005.
[8]ZAMBELLI C,VINCENZI T,OLIVO P.A compact model for erratic event simulation in flash memory arrays[J].IEEETransactions on Electron Devices,2014,11(61):3716-3722.
[9]CHIMENTON A,OLIVO P.Impact of high tunneling electric fields on erasing instabilities in NOR flash memories[J].IEEE Transactions on Electron Devices,2006,1(53):97-102.
[10]BEZ R,CANTARELLI D,MOIOLI L,et al.A new erasing method for a single-voltage long-endurance flash memory[J].IEEE Electron Device Letters,2002,2(19):37-39.
[2]YOSHIKAWA K,YAMADA S,MIYAMOTO J,et al.Comparison of current flash EEPROM erasing methods:Stability and how to control[C]//International Electron Devices Meeting.[S.l.]:IEEE,1992,93(74):595-598.
[3]WEI Dai-long,CAO Zi-gui,TANG Zhi-lin.An effective approach to improve split-gate flash product data retention[J].Journal of Semiconductor,2017,38(10):107-110.
[4]HEINRICH-BARNA S,DUNN C,VERRET D.Low temperature endurance failures on flash memory[C]//International Symposium on Quality Electronic Design.[S.l.]:IEEE,2017:87-92.
[5]SUN Zhong,ZHANG Man-hong,HUO Zong-liang.et al.Effect of damage in source and drain on the endurance of a65-nm-Node NOR flash memory[J].IEEE Transactions on Electron Devices,2013,12(60):3989-3995.
[6]TORRENTE G,COIGNUS J,VERNHET A,et al.Microscopic analysis of erase-induced degradation in 40 nm NOR flash technology[J].IEEE Transactions on Device and Materials Reliability,2016,4(16):597-603.
[7]SIKORA A,PESL F P,UNGER W.Technologies and reliability of modern embedded flash cells[J].Microelectronics Reliability,2006,46(12):1980-2005.
[8]ZAMBELLI C,VINCENZI T,OLIVO P.A compact model for erratic event simulation in flash memory arrays[J].IEEETransactions on Electron Devices,2014,11(61):3716-3722.
[9]CHIMENTON A,OLIVO P.Impact of high tunneling electric fields on erasing instabilities in NOR flash memories[J].IEEE Transactions on Electron Devices,2006,1(53):97-102.
[10]BEZ R,CANTARELLI D,MOIOLI L,et al.A new erasing method for a single-voltage long-endurance flash memory[J].IEEE Electron Device Letters,2002,2(19):37-39.