用于偏置电路的低纹波电荷泵设计（英文）
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摘要
提出了一种低电压CMOS工艺下用于偏置电路中的低漏电流电荷泵电路设计.漏电是输出纹波的主要来源,引入两个不同频率的时钟,通过控制电荷转移器件的开关交替动作来抑制反向漏电流.与传统设计相比,在每级电荷泵单元中增加了两个额外的MOS管,用于维持电荷泵单元中每个晶体管的衬底电位.详细分析了时钟和寄生所引入的非理想效应,并在0.35μm工艺下设计了一款电荷泵电路.仿真结果表明,所提出的9级电荷泵在1.4 V电源电压下能够实现13.4 V直流输出和0.17 mV纹波电压.这种电荷泵结构具有更好的噪声性能,可用于给传感器电路提供稳定的电压偏置.
A low ripple charge pump in low-voltage CMOS process is proposed for the bias circuit.Two clocks with different frequency are utilized to alternately turn on and off the charge-transfer devices to suppress the return-back leakage current, which could improve the output ripple. Compared with conventional designs, two more MOSFETs are added to each pump stage to maintain the correct bulk voltage of all MOSFETs. The non-ideal effects introduced by clock and technology parasitic are analyzed in detail, and the circuit has been designed with 0.35 μm technology. The simulation results show that the proposed nine-stage charge pump can obtain a 13.4 V DC voltage output with 0.17 mV ripple wave under VDD=1.4 V. With the improved noise performance, the proposed charge pump circuit is able to provide a stable high voltage bias for sensors.
A low ripple charge pump in low-voltage CMOS process is proposed for the bias circuit.Two clocks with different frequency are utilized to alternately turn on and off the charge-transfer devices to suppress the return-back leakage current, which could improve the output ripple. Compared with conventional designs, two more MOSFETs are added to each pump stage to maintain the correct bulk voltage of all MOSFETs. The non-ideal effects introduced by clock and technology parasitic are analyzed in detail, and the circuit has been designed with 0.35 μm technology. The simulation results show that the proposed nine-stage charge pump can obtain a 13.4 V DC voltage output with 0.17 mV ripple wave under VDD=1.4 V. With the improved noise performance, the proposed charge pump circuit is able to provide a stable high voltage bias for sensors.
引文
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3 Ying T R,Ki W H,Chan M.Area-efficient CMOS charge pumps for LCD drivers[J].IEEE Journal of SolidState Circuits,2003,38(10):1 721-1 725.
4 Jawed S A,Cattin D,Massari N,et al.A 1.8 V 828μW 80 dB digital MEMS microphone[J].Analog Integrated Circuits and Signal Processing,2011,67(3):395-405.
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6 Dickson J F.On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique[J].IEEE Journal of Solid-State Circuits,1976,11(3):374-378.
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9 Wu J T,Chang K L.MOS charge pumps for low-voltage operation[J].IEEE Journal of Solid-State Circuits,1998,33(4):592-597.
10 Ker M D,Chen S L,Tsai C S.Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes[J].IEEE Journal of Solid-State Circuits,2006,41(5):1 100-1 107.
11 Cabrini A,Gobbi L,Torelli G.Enhanced charge pump for ultra-low-voltage applications[J].Electronics Letters,2006,42(9):512-514.
12 Bhalerao S A,Chaudhary A V,Patrikar R M.A CMOS low voltage charge pump[C/OL]//20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems,Bangalore,India,Jan 6-10,2007.[2017-09-18].https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4092161.
13 New L F,Bin A A Z A,Leong M F.A low ripple CMOS charge Pump for low-voltage application[C/OL]//IEEE 2012 4th International Conference on Intelligent and Advanced Systems,Kuala Lumpur,Malaysia,June12-14,2012.[2017-09-18].https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6306120.
14 Weng Y H,Tsai H W,Ker M D.Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process[J].Microelectronics Reliability,2011,51(5):871-878.
15 Favrat P,Deval P,Declercq M J.A new high efficiency CMOS voltage doubler[C/OL]//IEEE Custom Integrated Circuits Conference,Santa Clara,CA,USA,May 5-8,1997.[2017-09-19].https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=606625.
16 Fantini A,Cabrini A,Torelli G.Impact of control signal non-idealties on two-phase charge pumps[C/OL]//IEEE International Symposium on Circuits and Systems,New Orleans,LA,USA,May 27-30,2007.[2017-09-19].https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4252947.
2 Atsumi S,Kuriyama M,Umezawa A,et al.A 16 Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation[J].IEEE Journal of Solid-State Circuits,1994,29(4):461-469.
3 Ying T R,Ki W H,Chan M.Area-efficient CMOS charge pumps for LCD drivers[J].IEEE Journal of SolidState Circuits,2003,38(10):1 721-1 725.
4 Jawed S A,Cattin D,Massari N,et al.A 1.8 V 828μW 80 dB digital MEMS microphone[J].Analog Integrated Circuits and Signal Processing,2011,67(3):395-405.
5 Pierre R S.Low-power BiCMOS op-amp with integrated current-mode charge pump[J].IEEE Journal of SolidState Circuits,2000,35(7):1 046-1 050.
6 Dickson J F.On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique[J].IEEE Journal of Solid-State Circuits,1976,11(3):374-378.
7 Choi K H,Park J M,Kim J K,et al.Floating-well charge pump circuits for sub-2.0 V single power supply flash memories[C]//Japan Society of Applied Physics and the IEEE Solid-state Circuit Society:Symp Vlsi Circuits Dig Tech Papers,June 12-14,1997,Kyoto,Japan.Tokyo:Business Center for Academic Societies Japan,1997:61-62.
8 Lai S Y,Wang J S.A high-efficiency CMOS charge pump circuit[C/OL]//2001 IEEE International Symposium on Circuits and Systems,Sydney,NSW,Australia,May 6-9,2001.[2017-09-17].https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=922259.
9 Wu J T,Chang K L.MOS charge pumps for low-voltage operation[J].IEEE Journal of Solid-State Circuits,1998,33(4):592-597.
10 Ker M D,Chen S L,Tsai C S.Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes[J].IEEE Journal of Solid-State Circuits,2006,41(5):1 100-1 107.
11 Cabrini A,Gobbi L,Torelli G.Enhanced charge pump for ultra-low-voltage applications[J].Electronics Letters,2006,42(9):512-514.
12 Bhalerao S A,Chaudhary A V,Patrikar R M.A CMOS low voltage charge pump[C/OL]//20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems,Bangalore,India,Jan 6-10,2007.[2017-09-18].https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4092161.
13 New L F,Bin A A Z A,Leong M F.A low ripple CMOS charge Pump for low-voltage application[C/OL]//IEEE 2012 4th International Conference on Intelligent and Advanced Systems,Kuala Lumpur,Malaysia,June12-14,2012.[2017-09-18].https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6306120.
14 Weng Y H,Tsai H W,Ker M D.Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process[J].Microelectronics Reliability,2011,51(5):871-878.
15 Favrat P,Deval P,Declercq M J.A new high efficiency CMOS voltage doubler[C/OL]//IEEE Custom Integrated Circuits Conference,Santa Clara,CA,USA,May 5-8,1997.[2017-09-19].https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=606625.
16 Fantini A,Cabrini A,Torelli G.Impact of control signal non-idealties on two-phase charge pumps[C/OL]//IEEE International Symposium on Circuits and Systems,New Orleans,LA,USA,May 27-30,2007.[2017-09-19].https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4252947.