FIR算法在可重构专用处理器中的并行化实现
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摘要
基于FIR算法在数字信号处理系统中的重要性以及当前对于高性能实时处理的需求,在一款可重构专用处理器平台上实现了FIR算法的并行化。并且对传统的直接型乘累加器进行了改进,提出了一种效率更高、延时更低的乘累加器,提高了FIR算法的性能。实验结果表明,设计的并行FIR滤波器误差在10~(-8)量级,对大于1 k点的FIR运算并行化效率达95%以上,加速比达3.85以上。
The significance of FIR algorithm in digital signal processing system and demand for high-performance real-time processing facilitates the realization of a parallel FIR filter on the reconfigurable processor and a new kind of multiply-accumulator featuring higherefficiency and lower time delay.Experiment shows that the error of the FIR filter is within 10~(-8)and the parallel efficiency reaches 95% and higher for FIR algorithm with over 1k point.
The significance of FIR algorithm in digital signal processing system and demand for high-performance real-time processing facilitates the realization of a parallel FIR filter on the reconfigurable processor and a new kind of multiply-accumulator featuring higherefficiency and lower time delay.Experiment shows that the error of the FIR filter is within 10~(-8)and the parallel efficiency reaches 95% and higher for FIR algorithm with over 1k point.
引文
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[2]王英喆,王振宇,严伟,时广轶.全并行FIR滤波器的FPGA实现与优化[J].电子设计工程,2015,23(22):94-97.
[3]赵文兵,杨建宁.FIR滤波器的FPGA实现及其仿真研究[J].微计算机信息,2005,21(7):108-109.
[4]虞希清.专用集成电路设计实用教程[M].杭州:浙江大学出版社,2007:1-4.
[5]Tian J,Li G,Li Q.Hardware-efficient parallel structures for linear-phase FIR digital filter[C].Circuits and Systems(MWSCAS),2013 IEEE 56th International Midwest Symposium on.IEEE,2013:995-998.
[6]Tsao Y C,Choi K.Hardware-efficient parallel FIR digital filter structures for symmetric convolutions[C].Circuits and Systems(ISCAS),2011 IEEE International Symposium on.IEEE,2011:2301-2304.
[7]Tsao Y C,Choi K.Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm[J].Very Large Scale Integration(VLSI)Systems,IEEE Transactions on,2012,20(2):366-371.
[8]Nikolaos S Voros,等编著.可重构片上系统的系统级设计System Level Design of Reconfiguable System-on-Chip(影印版)[M].北京:科学出版社,2007.
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