Improving the reliability of microprocessors under BTI and TDDB degradations.
详细信息
文摘
Reliability is a fundamental challenge for current and future microprocessors with advanced nanoscale technologies. With smaller gates,thinner dielectric and higher temperature microprocessors are vulnerable under aging mechanisms such as Bias Temperature Instability BTI) and Temperature Dependent Dielectric Breakdown TDDB). Under continuous stress both parametric and functional errors occur,resulting compromised microprocessor lifetime. In this thesis,based on the thorough study on BTI and TDDB mechanisms,solutions are proposed to mitigating the aging processes on memory based and random logic structures in modern out-of-order microprocessors. A large area of processor core is occupied by memory based structure that is vulnerable to BTI induced errors. The problem is exacerbated when PBTI degradation in NMOS is as severe as NBTI in PMOS in high-kappa metal gate technology. Hence a novel design is proposed to recover 4 internal gates within a SRAM cell simultaneously to mitigate both NBTI and PBTI effects. This technique is applied to both the L2 cache banks and the busy function units with storage cells in out-of-order pipeline in two different ways. For the L2 cache banks,redundant cache bank is added exclusively for proactive recovery rotation. For the critical and busy function units in out-of-order pipelines,idle cycles are exploited at per-buffer-entry level. Different from memory based structures,combinational logic structures such as function units in execution stage can not use low overhead redundancy to tolerate errors due to their irregular structure. A design framework that aims to improve the reliability of the vulnerable functional units of a processor core is designed and implemented. The approach is designing a generic function unit GFU) that can be reconfigured to replace a particular functional unit FU) while it is being recovered for improved lifetime. Although flexible,the GFU is slower than the original target FUs. So GFU is carefully designed so as to minimize the performance loss when it is in-use. More schemes are also designed to avoid using the GFU on performance critical paths of a program execution. Then finally the TDDB reliability issues are analyzed and bit flipping technique is designed in addition to voltage scaling to improve TDDB reliability in memory based and combinational logic structures,leveraging TDDBs dependence on bit flipping frequency. The update counts in multiple units include matrix scheduler,caches and TLBs indicate significant potential of utilizing bit flipping circuit to mitigate TDDB stress. Although applying bit flipping technique on entry update improves the reliability under TDDB stress in most units,ITLB is the only unit that lacks natural frequent update activity. The local write circuit is a effective and light weight design to proactively boost the bit flipping frequency.