Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs

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• 作者：Jan Moritz Joseph ; ^a ; ^{jan.joseph@iovgu.de} ; Author Vitae ; Christopher Blochwitz^b ; ^{blochwitz@iti.uni-luebeck.de} ; Author Vitae ; Alberto Garcí ; a-Ortiz^c ; ^{agarcia@item.uni-bremen.de} ; Author Vitae ; Thilo Pionteck^a ; ^{thilo.pionteck@ovgu.de} ; Author Vitae
• 关键词：Network-on-Chip ; Heterogeneous 3D-System-on-Chip ; Asymmetric 3D-Noc ; Buffer reorganization ; Buffer depths
• 刊名：Microprocessors and Microsystems
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：48
• 期：Complete
• 页码：36-47
• 全文大小：1177 K
• 卷排序：48

文摘

In this paper we investigate the effects of asymmetric organization and depths of Network-on-Chip (NoC) router buffers among dies in heterogeneous 3D-System-on-Chips (SoCs). In our novel approach the properties of the routers are aligned with the characteristics of the technological nodes per layer. We call these designs Asymmetric 3D-NoCs (A-3D-NoCs). In this work we demonstrate potentials of A-3D-NoCs in comparison to a conventional, symmetric 3D-NoC: Applying asymmetric buffer reorganization we achieve area savings of 8.3% and power savings of 5.4% for link buffers while accepting a minor average system performance loss of 2.1%. With additional asymmetry in buffer depth up to 28% cost savings and 15% power reduction are given in combination with a 4.6% performance decline. Thus, the proposed buffer organization scheme is applicable for cost and power critical applications of NoCs in heterogeneous 3D-SoCs.